Circuit Design

16 Gbps high-speed I/O link
16 Gbps high-speed I/O link over a lossy backplane channel in Cadence Virtuoso (65 nm CMOS)
16 Gbps high-speed I/O link
30 Gbps Silicon Photonics link
30 Gbps SiP data transmission link in Cadence Virtuoso (65 nm CMOS)
30 Gbps Silicon Photonics link
Sub-Sampling LC-PLL design
Design, Analysis and Simulation of a Frequency Synthesizer using Analog Sub-Sampling LC-PLL (65 nm CMOS)
Sub-Sampling LC-PLL design
Two-Stage OTA design using gm/Id methodology
Two-Stage OTA design and analysis using gm/Id methodology (45 nm CMOS).
Two-Stage OTA design using gm/Id methodology
SiEPICfab Shuksan PDK
Developed from scratch a new PDK using in-house developed layermap and technology files
Link
SiEPICfab Shuksan PDK
Voltage Controlled Oscillator (VCO)
Comparison of different VCO designs for PLLs
Voltage Controlled Oscillator (VCO)
6T SRAM memory cell design and layout
6T SRAM memory cell design and layout in 65nm node
6T SRAM memory cell design and layout
Variable frequency divider
Variable frequency divider for PLLs with a logic circuit to switch between different frequency bands
Variable frequency divider
Clock distribution network
Designed clock distribution network using numerous buffer stages to minimize the delay, rise and fall times, skew, and power consumption of the network
Clock distribution network
Error Amplifier in LDO
Analysis of the role of Error Amplifier in the context of Low-Dropout Voltage Regulators.
Error Amplifier in LDO