We present a methodology for data-driven and bidirectional Verilog-A model development for Silicon Photonics devices. The approach enables s-parameter based measurement-backed models that support electro-optic co-simulation with electronic circuits in Cadence Virtuoso, including bidirectional signal flow, DWDM signalling, and Monte-Carlo simulations.

Designing subject-independent Brain-Computer In- terfaces remains to be an open question for developing systems that can capture the inter-subject intrinsic brain features and classify them with reasonable accuracy. This paper presents the application of the state-of-the-art deep transfer learning archi- tectures on classifying ERP signals. We report 66.87%, 67.64%, 65.58%, and 71.93% test classification accuracy for DenseNet121, DenseNet201, Xception, and VGG-16 models, respectively. The experimental results demonstrate the viability of our approach in subject independent ERP-signals classification and suggest the better performance of models with fewer layers in classifying ERP signals.

This work proposes electro-optical design of logic gates using micro-ring resonators (MRR). We achieve this through various combinations of MRRs. In order to modulate the rings, thermo-optic effect is utilized. The reported devices are completely CMOS-compat- ible and can be fabricated using existing technologies. We also provide static responses to explain the device working principles. By plotting dynamic response spectra, the per- formance of each device is examined. The proposed logic elements are able to operate at 0.4 Mbps.

In the past few years, Back-End-of-Line (BEOL) Nano-electromechanical (NEM) relays have emerged as promising switching devices for the beyond-CMOS era, due to their zero- leakage current property, and the compatibility to CMOS fabrication processes. Though the mechanical movement causes the relays to be inherently slower than transistors, the metallic contact interface untethers the limitation on gate-to-drain voltage, which makes the relays capable of handling higher voltages. In this work, we propose novel designs for BEOL NEM relay-based inductorless DC-DC converters for on-chip voltage conversions. The design, implementation, and analysis of buck (step-down) and boost (step-up) converters are shown. Both converters consist of only four NEM relays, respectively. By utilizing the charge pump topology in a switched-capacitor configuration, the relay converters exhibit lower output ripple and higher efficiency compared to their CMOS counterparts. This is particularly valuable for DC-DC voltage conversions in the Internet of Things chips, where the converter switching frequency is moderate, while the demands for efficiency, area saving, and on-chip integration are high.