Hi! I’m Dias, a graduate student at the Department of Electrical and Computer Engineering in UBC. Right now I’m conducting research on the topic of cosimulation of electronic circuits along with Silicon Photonics devices for various applications (e.g. optical data transmission links). Generally, my research interests include CMOS electronics, Silicon Photonics, and applied Machine Learning. This website is intended to serve as a place where you can see all my projects and past experience. Soon I am planning to write blogs on the topics that interest me. Feel free to get in touch with me via email or using the form at the end of this page.
MASc in Electrical and Computer Engineering, November 2023 (expected date)
University of British Columbia
BEng in Electrical and Electronic Engineering, 2020
Nazarbayev University
16 Gbps high-speed I/O link over a lossy backplane channel in Cadence Virtuoso (65 nm CMOS)
30 Gbps SiP data transmission link in Cadence Virtuoso (65 nm CMOS)
Design, Analysis and Simulation of a Frequency Synthesizer using Analog Sub-Sampling LC-PLL (65 nm CMOS)
Two-Stage OTA design and analysis using gm/Id methodology (45 nm CMOS).
Developed from scratch a new PDK using in-house developed layermap and technology files
Built an HDR image upscaling GAN (8x upscaling) in PyTorch using ESRGAN architecture as a reference
Comparison of different VCO designs for PLLs
6T SRAM memory cell design and layout in 65nm node
Variable frequency divider for PLLs with a logic circuit to switch between different frequency bands
Designed clock distribution network using numerous buffer stages to minimize the delay, rise and fall times, skew, and power consumption of the network
Python algorithm for equal distribution of sensors among base stations
Automating cancer detection & classification using pre-trained CNNs
Apparent Age, Gender and Ethnicity Prediction using Deep Learning techniques
Real-time face recognition system on Raspberry Pi 3 for automated attendance monitoring
Analysis of the role of Error Amplifier in the context of Low-Dropout Voltage Regulators.
Designing subject-independent Brain-Computer In- terfaces remains to be an open question for developing systems that can capture the inter-subject intrinsic brain features and classify them with reasonable accuracy. This paper presents the application of the state-of-the-art deep transfer learning archi- tectures on classifying ERP signals. We report 66.87%, 67.64%, 65.58%, and 71.93% test classification accuracy for DenseNet121, DenseNet201, Xception, and VGG-16 models, respectively. The experimental results demonstrate the viability of our approach in subject independent ERP-signals classification and suggest the better performance of models with fewer layers in classifying ERP signals.
This work proposes electro-optical design of logic gates using micro-ring resonators (MRR). We achieve this through various combinations of MRRs. In order to modulate the rings, thermo-optic effect is utilized. The reported devices are completely CMOS-compat- ible and can be fabricated using existing technologies. We also provide static responses to explain the device working principles. By plotting dynamic response spectra, the per- formance of each device is examined. The proposed logic elements are able to operate at 0.4 Mbps.
In the past few years, Back-End-of-Line (BEOL) Nano-electromechanical (NEM) relays have emerged as promising switching devices for the beyond-CMOS era, due to their zero- leakage current property, and the compatibility to CMOS fabrication processes. Though the mechanical movement causes the relays to be inherently slower than transistors, the metallic contact interface untethers the limitation on gate-to-drain voltage, which makes the relays capable of handling higher voltages. In this work, we propose novel designs for BEOL NEM relay-based inductorless DC-DC converters for on-chip voltage conversions. The design, implementation, and analysis of buck (step-down) and boost (step-up) converters are shown. Both converters consist of only four NEM relays, respectively. By utilizing the charge pump topology in a switched-capacitor configuration, the relay converters exhibit lower output ripple and higher efficiency compared to their CMOS counterparts. This is particularly valuable for DC-DC voltage conversions in the Internet of Things chips, where the converter switching frequency is moderate, while the demands for efficiency, area saving, and on-chip integration are high.